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> Use&of&FPGA&Model-Based&Design&Flow&for&Motor&Control&on&Servo&Dr…
Use of FPGA Model-Based Design Flow for Motor Control on Servo Drives
10:27:19 来源:PCIM
　　Kevin Smith, Altera Europe Ltd, UK,
　　The Power Point Presentation will be available after the conference.
　　Abstract
　　Many designers are using model-based design tools for industrial applications yet few use
　　them with direct to hardware implementation flows. In conjunction with MATLAB/Simulink,
　　the Altera& DSP Builder Advanced Blockset provides a behavioral modeling flow with auto
　　mated VHDL generation which supports algorithms designed in floating point, variable preci
　　sion fixed point or a combination. DSP builder generates optimized FPGA hardware with fully
　　predictable latency and provides the designer control to trade off FPGA resource usage
　　against algorithm latency.
　　The model based FPGA design flow is applied to the current control algorithm of an AC ser
　　vo drive and the design flow and results discussed. Where the algorithm latency requires re
　　ducing further a technique for removing the processor entirely from the control loop is proposed.
　　1. Introduction
　　Model-based design tools are becoming increasingly popular in shortening design cycles for
　　industrial drive control. MATLAB/Simulink is one of the most commonly used and supports a
　　number of automated flows that can take a design from initial system modeling to implementation.
　　The Altera DSP Builder Advanced blockset [3] provides a MATLAB/Simulink flow that
　　allows designers to create hardware optimized fixed latency representations of algorithms
　　without requiring HDL/hardware skills.
　　In this paper we will discuss the model-based design flow for FPGA detailed in fig. 1, and its
　　application to Field Oriented Control (FOC) motor control for servo drives. Section 2 discusses
　　the “Model System” step, sections 3 & 4 discuss the “Optimize Algorithm in Hardware”
　　step, sections 5 & 6 cover the “Integration in Hardware” step and section 7 covers results
　　& analysis.
　　The FalconEye FPGA Motor Control reference solution [5] demonstrates the use of FPGAs
　　for the implementation of FOC for AC servo motors. The FPGA design included in the solution
　　contains peripheral interfaces in Hardware Description Language (VHDL) for position
　　encoders (EnDat, Biss, Resolver) and ∑∆ ADCs for current feedback, and a 3-channel
　　Space Vector Pulse Width Modulation (PWM) output for AC Voltage control implemented on
　　an Altera Cyclone& IV FPGA. In the design a Nios& II soft-processor is used to implement a
　　„C‟ based Interrupt Service Routine (ISR) to control the interface IP and run the FOC current
　　control algorithm plus speed and position control loops, fig. 2.
　　Fig. 2. Motor control implementation on FalconEye.
　　2. Field Oriented Control Algorithm Design
　　As a case study for the model-based FPGA design flow, fig. 1, for motor control the FOC
　　current control algorithm from FalconEye was modeled and implemented using Altera DSP
　　Builder Advanced blockset in MATLAB/Simulink. This involved implementation of Forward &
　　Reverse Clarke and Park transforms, Direct & Quadrature current Proportional Integral (PI)
　　Control loops, Sin/Cos & saturate functions in the DSP builder blockset. To verify correctness
　　of the algorithm, behavioral simulation of the DSP Builder model was carried in MATLAB/Simulink
　　with a simple Permanent Magnet Synchronous Machine (PMSM) motor model
　　to verify the correctness of the algorithm.
　　The top level of the Simulink model is a testharness consisting of standard Simulink blocks
　　implementing the motor model & control inputs. The next level consists of speed/position
　　control loops and Space Vector Modulation algorithm in standard Simulink blocks and the
　　FOC block. The FOC block level of the model was implemented in the DSP Builder advanced
　　blockset which allow algorithm simulation as well as VHDL generation. The testharness,
　　speed/position control loops & FOC blocks are all shown in fig 3. To simplify the simulation
　　model the PWM, ADC and position encoder were all assumed to be ideal and modeled
　　as direct connections.
　　Fig. 3. Simulink Test Harness & FOC model combining Simulink & DSP builder blocksets
　　FOC involves controlling the motor‟s sinusoidal 3-phase currents in real time to create a
　　smoothly rotating magnetic flux pattern, where the frequency of rotation corresponds to the
　　frequency of the sine waves [2]. The technique controls the amplitude of the current vector
　　to maintain its position at 90 degrees with respect to the rotor magnet flux axis (“quadrature”
　　current). This allows designers to control torque while keeping the “direct” current component
　　(0 degrees) at zero. The algorithm involves the following steps:
　　1. Convert the 3-phase feedback current inputs and the rotor position from the encoder into
　　“quadrature” and “direct” current components using Clarke and Park transforms.
　　2. Use these current components as the inputs to two proportional and integral (PI) controllers
　　ers running in parallel to limit the “direct” current to zero and the “quadrature” current to the
　　desired torque.
　　3. Convert the “direct” and “quadrature” voltage outputs from the PI controllers back to 3phase
　　voltages with inverse Clarke and Park transforms.
　　The results of the simulation for a position control scenario are shown in fig. 4. The monitor
　　points for the simulation waveforms match up with the red circular markers shown in fig 3.
　　Fig. 4. Simulink simulation output of FOC with step position request of 3
　　3. Using DSP Builder advanced blockset
　　DSP Builder advanced blockset supports bit-accurate simulation and VHDL generation of the
　　full range of fixed-point and floating point data types available in Simulink. Using floating
　　point can have benefits such as offering high dynamic range and ease of use by avoiding
　　arithmetic overflows and the manual floating point to fixed point conversion & scaling steps
　　that are often necessary in algorithm development. The data types used can subsequently
　　be optimized to adjust hardware usage and calculation latency, and Simulink simulations run
　　to confirm adequate performance.
　　After the algorithm has been developed in Simulink, DSP builder can automatically generate
　　pipelined HDL that is targeted and optimized to the chosen FPGA device. This VHDL can be
　　used in a HDL simulator such as ModelSim to verify the generated logic vs. Simulink and in
　　the Altera Quartus& II software to compile to hardware. Instant feedback of the VHDL‟s logic
　　utilization and algorithm latency is given in automatically generated Simulink reports.
　　The algorithm is designed in Simulink using the DSP builder blockset in a “flat” parallel form
　　that can receive and process new input data every sample time. However, in designs which
　　have a much lower sample rate than the FPGA clock rate, such as this FOC design (16kHz
　　vs 100MHz), DSP Builder advanced blockset‟s logic “folding” functionality can be used to
　　trade off an increase in algorithm latency for a decrease in the used FPGA resources. This
　　allows easy use of as much hardware parallelism as necessary to reach the target latency
　　with the most cost effective use of FPGA resources without making any changes to the algorithm.
　　The logic “folding” feature of DSP Builder re-uses physical resources such as multipliers and
　　adders for different calculations with the VHDL generation automatically handling the complexity
　　of building the time division multiplexed hardware for the particular sample to clock
　　rate ratio, fig. 5. Logic “folding” also supports the processing of multiple channels of input data
　　allowing designs to easily be parameterized from one to multiple channels and the implementation
　　automatically generated.
　　Fig. 5. Unfolded and Folded Hardware Examples
　　4. Optimizing the Algorithm Implementation
　　The FOC algorithm was initially modeled in single precision floating point. The logic “folding”
　　feature of DSP Builder was benchmarked against normal operation. Using “folding” showed
　　a significant Logic Element (LE) & Multiplier usage reduction by trading this off against an increase
　　in latency, fig. 6.
　　Before folding had been applied to the floating point design this algorithm would have required
　　a substantially larger and more expensive FPGA. With folding the LE & Multiplier re-
　　sourceswere reduced significantly by 50% and 90% respectively yet the latency was still
　　within the design target of under 5us.
　　The original software based FalconEye design used 16-bit data types and 32-bit accumulators
　　as these were a good match for the 32-bit Nios II processor. An exact match was
　　achieved with DSP Builder by using Simulink sfix16_en10 (16bit - Fixed point with 1 sign, 5
　　integer + 10 fractional bits) data types. To investigate how DSP Builder systems scale with
　　different arithmetic precisions both 16-bit & 32-bit fixed-point implementations were created,
　　fig. 6. As all 3 data types had sufficient accuracy for the FOC algorithm being used each implementation
　　n performed similarly in simulation and in hardware.
　　The FPGA resource usage for the DSP Builder generated logic and the algorithm latency
　　were measured in each case. The fixed point versions had significantly lower Logic Element
　　(LE) and multiplier usage and lower latency than the floating point version. The 16-bit fixed
　　point version had half the LE usage and much lower multiplier usage than the 32-bit version.
　　5. Interfacing with a Processor
　　The DSP builder generated VHDL has a signal interface that matches the connections in
　　Simulink. In the FOC model this meant that feedback currents, position feedback, torque
　　command and gain parameters were all parallel inputs into the system and voltage commands
　　were parallel outputs. To allow direct connectivity to the Nios II soft processor these
　　parallel inputs & outputs were terminated by an Avalon-MM (Avalon Memory-Mapped) register
　　map, fig. 7. The address map is declared by connecting DSP Builder Avalon Register
　　blocks to the parallel input and output signals. Some additional handshaking logic (not
　　shown) was also added to allow the DSP builder system to be started after all input values
　　are set up and wait for the calculation to finish before the output values are read. In the generated
　　VHDL the parallel I/O was no longer externally visible and terminated by a single Avalon-MM
　　slave processor interface with addressable registers.
　　Fig. 7. FOC model integrated in Simulink with Avalon-MM register map
　　6. System Integration with Qsys and Nios II soft processor
　　The DSP builder generated VHDL block with Avalon-MM interface can now be integrated
　　with the rest of the motor control system in the Altera Qsys system integration tool, fig.8. Rather
　　than using traditional HDL design methods to define and connect HDL modules manually,
　　Qsys allows definition of system components in a GUI and then generates the interconnect logic
　　automatically.
　　Fig. 8. Qsys generated system integrating all components
　　To run the DSP Builder design as part of the drive algorithm a „c‟ wrapper was written to
　　pass the data values between the Nios II and DSP builder hardware. The DSP Builder handshaking
　　logic described earlier is used to ensure synchronization between the software &
　　hardware. The software sets up any changes to hardware parameters such as PI gains,
　　writes new feedback currents, position feedback and torque command input data before
　　starting the DSP builder calculation. The software then waits for the DSP builder calculation
　　to finish before reading out the new voltage command data.
　　The call to the „C‟ wrapper was inserted in the original Nios II Interrupt Service Routine (ISR)
　　that runs the FOC algorithm with an option to switch between software and DSP Builder implementations
　　at runtime, fig. 9.
　　Fig. 9. Example „C‟ wrapper to interface DSP Builder components with Nios II processor
　　7. Verifying Runtime Performance in Hardware
　　The DSP Builder generated hardware was tested on the motor control kit and the ability to
　　dynamically switch between software, fixed-point and floating-point DSP Builder implementations
　　added to the Nios II ISR. The latency of each implementation was measured by software
　　performance counters, fig. 10. All implementations controlled the motor satisfactorily as
　　per the Simulink simulations.
　　Fig. 10. Algorithm latency measurements for different implementations
　　The latency of the Nios II implementation was dominated by the fixed-point sin/cos functions
　　which took 3 &s. It was noted that there was a fixed overhead of 0.75 &s for moving the data
　　to and from the Nios II processor and DSP Builder hardware over Avalon-MM (6 writes and 3
　　reads), and also that the ISR took 0.93 &s to start running after the interrupt occurred.
　　To provide a solution with a reduced total latency the processor could be removed entirely
　　from the FOC control loop, using instead a Direct Memory Access (DMA) controller programmed
　　to move the data directly from the current & position feedback peripherals to the
　　FOC block and then from the FOC block to the PWM peripheral. Using the DMA would make
　　runtime of the complete algorithm 100% deterministic as well as reducing the total latency.
　　The Avalon-MM latency would reduce from 0.75 &s to 0.15 &s and the 0.93 &s delay incurred
　　by the processor entering the ISR would be removed, so reducing the total latency by 1.5 &s.
　　8. Summary
　　The use of DSP Builder advanced blockset in conjunction with MATLAB/Simulink provides a
　　bit-accurate model-based algorithm design flow with behavioral design entry and direct compilation
　　to hardware via VHDL. The generated hardware has a fully deterministic latency
　　which is known at the algorithm modeling stage. The “folding” feature allows the generated
　　VHDL to use as much hardware parallelizm as necessary to achieve the desired algorithm
　　latency whilst minimizing FPGA resource usage. The generated DSP Builder component can
　　easily be integrated without the need for any hand-written VHDL in Qsys along with the Nios
　　II processor, DMA controller and a range of peripheral IP necessary for AC motor control.
　　9. Literature
　　[1] J. O. Krah, C. Klarenbach: “FPGA based Field Oriented Current Controller for High Performance
　　Servo Drives”, PCIM Conference, Nürnberg, 2008
　　[2] Zhang X Geng Y Zhang Mu; “The Research of Digital Vector Control Driver of
　　Permanent Magnet Synchronous Machine”, Control Automation and Systems Engineering
　　(CASE) 2011
　　[3] Altera DSP Builder Advanced Blockset,
　　[4] Altera Qsys System Integration Tool,
　　[5] EBV, FalconEye FPGA,
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