NanGate Open Cell Library
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求助，有人用过NangateOpenCellLibrary这个库在DC中综合过吗？我用它综合时，不能综合出扫描触发单元来，请问用过的大侠，这个库可以综合出扫描触发器吗？我用compile -scan 就会出现[p=30, 2, left]Warning: No scan equivalent exists for cell DFF_0/Q_reg (DFF_X1). (TEST-120)[/p][p=30, 2, left]请问该怎么办？还是这个库根本就综合不出扫描触发器来？[/p][p=30, 2, left]急需帮助！谢谢！！！[/p]
我在做DC综合时，用了一个45nm的新库，插入扫描链，在compile -scan 后，并没有扫描触发器，提示说库里没有扫描触发单元。可是同样的脚本，用smic18综合时是对的呀？我看了smic18库里有D触发器及加了扫描的触发器，我用的新库里，我也查了，也有普通的D触发器和带扫描的触发器，可是用新库时提示说库中没有扫描单元，它把原件综合成了DFF开头的一个普通D触发器，而没有综合成库里有的带扫描的SDFF开头的触发器，为什么呀？求助大哥大姐们，谢谢啦，要给老师交差，急！！！谢谢！！！From Vlsiwiki
To use the Cadence tools, you must change this environment variable:
export OSUcells=/mada/software/techfiles/osu_soc_v2.7/cadence
The OSU scripts for Cadence can be copied from here:
cp -rf /mada/software/techfiles/osu_soc_v2.7/cadence/flow/ami035
but they are for an old version of Encounter. Quite a few things have changed, so I am posting a description of the working script I made by modifying the old OSU scripts.
You will need to specify the correct top-level name and gate-level netlist name in encounter.conf. This keeps variables and constants used in the placement and routing scripts.
To run encounter, you simply can run:
at the Linux shell prompt.
In this tutorial, I may not explicitly mention the GUI menu commands, because it is more convenient to use the shell interface. However, most of these commands are available (with forms for options) under the appropriate menus (e.g. Timing, Place, Floorplan, etc.). I suggest that you use the GUI for the first time along with the "-cmd foo.log" argument to save your actions/commands to a file called foo.log. You can then create a script from the saved file.
To run a script, type:
encounter -init encounter.tcl
with X11 exported to your local machine. If this completes successfully, you can hit "f" to center the layout.
In the terminal window where you ran encounter, you should see the shell prompt:
encounter 1&
This is where you enter commands if you do not use the GUI.
A typical design flow involves subsequently refined layout steps. The first step is a course planning of the chip called floorplanning. This is followed by IO and cell placement, special net routing, clock tree synthesis, in-place optimization, and finally global and detailed routing.
Between most of these steps we perform a timing analysis on the circuit to determine its performance and see if we need to back up. The timing analysis is run with the following commands:
buildTimingGraph
timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS
The options to the command timeDesign will change depending on which part of the flow you are in.
Your design is read in by modifying the .conf file in the flow. There are specific lines to specify: the IO pads (.io), the input netlist (.mapped.v), the Synopsys design constraint file (.sdc), the timing library format (.tlf) file, the layout exchange format (.lef) file (which is the actual cell pins and boundaries), and numerous other parameters. This is loaded with the following command:
loadConfig ./encounter.conf
commitConfig
The floorplan stage defines the rows that the standard cells will go in. For small designs, it is sufficient to make a single floorplan and place everything in the hierarchy at once. This is called "flat" placement. If you have a large design or memories, you may have to customize this floorplan a little more by specifying the relative locations and sizes of the different blocks (sub-modules of your entire design) and the locations of the fixed size memories.
You can create a flat floorplan like this:
floorplan -r 1.0 0.9 1 1 1 1
This says that it should have a 1.0 aspect ratio (height to width), 90% row utilization, and have space of size "1" around the core. (This is probably in the default units specified in the .lef file.)
After you specify the rows, you also need to specify how the vdd and gnd signals connect to the rows. This is done by adding a power ring around the perimter of the design and stripes internal to the design. To really know the size of these wires, you will have to do power grid analysis after placement. This is not required in this project.
addRing -spacing_bottom 10 -width_left 10 -width_bottom 10 -width_top 10 -spacing_top 10 -layer_bottom metal3 -width_right 10 -around core -center 1 -layer_top metal3 -spacing_right 10 -spacing_left 10 -layer_right metal4 -layer_left metal4 -nets { gnd vdd }
-set_to_set_distance 100 -spacing 5 -xleft_offset 50 -layer metal4 -width 5 -nets { gnd vdd }
After the power is specified, you can place the cells in your design using the following command:
placeDesign
Once the cells are placed, you can connect the power stripes and rings to the standard cell rows.
sroute -noBlockPins -noPadRings
You should also perform a trial routing to see if any cell pins are inaccessible due to power routing:
trialroute
At this time, it is a good idea to do Pre-CTS Timing Analysis:
buildTimingGraph
timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS
This will give you an idea if your placement is way off and there is no chance for timing. If this is the case, you can first try to do "in place" optimization to fix the timing. This is done with the following commands:
optDesign -preCTS
If that doesn't meet timing, you will have to change your IO assignment or change your floorplan.
The previous timing analysis used an "ideal clock" with zero skew since the clock was not implemented yet. You can now create a clock tree using the following commands:
createClockTreeSpec -output encounter.cts
addCTSCellList CLKBUF1 CLKBUF2 CLKBUF3
clockDesign -clk clk
where your clock is named "clk". You can investigate the results of the clock tree synthesis (CTS) by
extracting the clock wire parasitics and analyzing the clock tree:
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
This is now a good time to check the timing of your placement with a real clock tree. The clock synthesis could have moved some cells to place clock buffers
or could have too much skew to meet timing:
setAnalysisMode -checkType setup -asyncChecks async -skew true -clockPropagation sdcControl
buildTimingGraph
timeDesign -postCTS -numPaths 10 -prefix postCTS
If there are problems with the timing, you can perform a post-CTS in-place optimization with a new parasitic mode to include the clock design:
setExtractRCMode -engine preroute -assumeMetFill
optDesign -postCTS
Then you can check timing again:
buildTimingGraph
timeDesign -postCTS -numPaths 10 -prefix postCTS
At this point, you will have to add "filler" cells wherever there are no cells so that the power rails in the rows are connected. These filler cells often also have "fill" material to improve CMP by increasing density of different layers:
addFiller -cell FILL -prefix FILL -fillBoundary
Your placement is now fixed and you need to begin the routing.
You first must specify how to connect the special pin types in the library:
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -override
Then you can route the entire design:
globalDetailRoute
and perform post-routing timing analysis:
setExtractRCMode -engine postRoute
buildTimingGraph
timeDesign -postRoute
along with an optional in-place routing optimization:
optDesign -postRoute
At this point, you should perform a final "sign-off" timing analysis inside Encounter using accurate parasitic extraction:
setExtractRCMode -engine signOff
buildTimingGraph
timeDesign -signOff
Right now, this is not working because we do not have "qrc" (the extractor) installed properly. You can use "-postRoute" instead for now.
You should also make sure there are no geometry (DRC) or connectivity (LVS) errors:
verifyGeometry
verifyConnectivity -type all
Note that for a real final design, you would perform DRC and LVS in Virtuoso much like you did in the custom design homeworks.
As a final step, you can save the layout:
streamOut final.gds2 -mapFile gds2_encounter.map -stripes 1 -units 1000 -mode ALL
(for streamOut to work the file gds2_encounter.map must be in the folder you run encounter in)
and the modified Verilog netlist:
saveNetlist -excludeLeafCell final.v
and the parasitics for all of your routing:
rcout -spf final.dspf
The gds2 file is sent to a fabrication plant for manufacturing while the final.v and final.dsp files are used for your sign-off timing analysis in Primetime.
.lib/.db - Synopsys "liberty" file for Design Compiler. This contains information about the logic function, timing, and power of all the cells in your library. The db file is just a compiled (binary) version.
.lef - Cadence Library Exchange Format for Encounter. This contains the geometric information about your library cells such as pin locations/layers, boundary, and routing blockages.
.tlf - Timing Library Format for Encounter. This contains the timing information of the library cells.
.tcl/.scr - TCL scripts that could be for Design Compiler, Encounter, or Primetime.
.v/.mapped.v - The unsynthesized and synthesized (gate-level) netlist, respectively.
.io - A proprietary file for Encounter that specifies which IO pads should be used for which IOs on your top module.
.sdc - Synopsys Design Constraints. This is a file that contains the definitions of your clocks, input/output delays and other design constraint information to pass between tools. Synopsys saves this file after you set up the constraints and Encounter/Primetime can read the file later so that the same constraints are used.
If you want to synthesize a design using the Nangate FreePDK45 cell library, you need to make a few changes:
1) You need to compile the Nangate .lib into a .db and use that. To do this, run:
dc_shell-t
Then execute these commands:
read_lib /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib
write_lib NangateOpenCellLibrary
which will create a file NangateOpenCellLibrary.db. Move that to your project directory.
Then, these lines change to the compile_dc.tcl:
set search_path [concat
$search_path . ]
set link_library [set target_library [concat
[list NangateOpenCellLibrary.db ] [list dw_foundation.sldb]]]
3) In the encounter.conf, you need to reference the .lib file instead of the .tlf file. You also need to point to the .lef file. Specifically, these lines change:
set OSUcells /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07
set rda_Input(ui_timelib) "$OSUcells/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib"
set rda_Input(ui_leffile) "$OSUcells/lef/NangateOpenCellLibrary.lef"
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This page was last modified on 14 March 2011, at 14:54.Search Engine
90 Threads found : Vcs Error
Don't have vcs docu at my disposal right now. Inside it search for the error with string : UCLI-003
I compiled my verilog codes with test bench files using vcs command. Then ./simv command is used to run simulation and it is also running without no errors and giving expected display messages in command window. vpd dump file is also created(amount of bytes of the vpd file is very low - 22KB). But when i view the wave form using dve command all the
I was performing simulation(scan_serial) in synopsys vcs for one block named rx_pd after performing pattern retargetting.
I got an error saying that Mismatch occurred
Signal name: SEL_VAUX_B
timestamp : 31290ns
instance :
topmodule/submodule/core/edt_rx_pd_channel2
Simulated : x
Expected : 1
The signal is found in topmodule,
50 modules and 2 UDPs read.
However, due to incremental compilation, no re-compilation is necessary.
make: Entering directory `/ufs/vlsi/nks45/RISCV/rocket-chip/vsim/csrc'
make: Warning: File `filelist.cu' has modification time 2 s in the future
ld -shared
-o objs/udps/zTfCi.o ob
I'm trying to install Synopsys vcs (MX) on an Ubuntu 64 bit server (version 14.04).
Once vcs is installed and bash variables (licence, PATH, vcs_HOME) has been set, when i try to compile a simple verilog test file i get:
$ vcs test.v -full64
Warning- Unsupported Linux version
Linux version '' is not supported
I have a Xilinx VHDL IP which I am compiling along with other Verilog and SV design files. I am compiling the VHDL design files first.
Prior to compiling the VHDL design files, I have compiled the Xilinx VHDL libs using the command:
compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_li
My design has Verilog and VHDL modules along with Xilinx primitives.There are no problems with the Xilinx Verilog libs. I have also compiled all the Xilinx VHDL libraries (a dir has been created with the compiled libs and I also have an error free log file. I had used the Xilinx command COMPXLIB for compilation of the Xilinx VHDL libraries).
I cannot figure out why vcs is throwing this error. Given below is the error message and then part of the code where error occurs.
vcs error message:
error- Unknown or bad value for genvar (...)
Send me the source code if possible, I'll try to compile it my vcs environment.
I have an encrypted RTL (encrypted using the synopsys Public key and cadence ncprotect utility.
But when trying to compile the protected file ,I get the following error,
Warning- Unterminated string
Unterminated string found in file 'adder_aec.vp'
at line '9'
for an argument 'IST"
`pragma protect data_method
Hi Friends
can you help me, how to solve the following error(Timing Violation) while running vcs simulation
Chronologic vcs simulator copyright
Contains Synopsys proprietary information.
Compiler version E-2011.03-SP1; Runtime version E-2011.03-SP1;
Nov 12 18:32 2014
Doing SDF annotation ...... Done
LEON-2 generic testben
We have mixed language design, hence we use vlogan but I get the same errors with the below command:
vlogan +v2k
-sverilog +libext+.v+.mdl
+incdir+/rtl/include
-timescale=1ns/10ps
error- Incorrect Logical Worklib or Reflib
The incorrect logical lib is "work".
Please check your Synopsys setup file.
In the rep
Here is one way to do it:
1) Compile your C code with GCC or G++
2) Next, if the C code was compiled with x86_64 bit. Thus, to make it vcs simulator compatible with the generated C library file (*.o, *.so) use this line of command:
vcs -full64 -sverilog -R +define+VCD -f ../../sim/filelist.f clk_xactor.o
Hope it helps.
Hi friends
Please help me help in following question
Run vcs simulation reading in a SDF file to simulate the IU(Integer Unit in LEON2 Processor) with C programs, find the number of clock cycles and timing error coverage
My tools environment is : installv3.0 , scl10.9.3 vcs2012, nanosim2012
I have already run vco of nanosim examples, it's passed.
But when I run NS-vcs in tutorial of nanosim examples, there was a error after "simv +COMPILE" command:
***** Warning: Stacksize soft limit 10240 K is too small, we prefer more than 60000 K, (...)
when I try to use vcs Save/Restart simulation feature in my design, the Denali MMAV model report some error like this:
*Denali* error: Checkpoint, Save/Restart disabled.
I think I have to add some
code to Denali PLI routines, but I can't find the solution in the MMAV userguide, Could anybody help me?
I use vcs program from synopsys for verilog code compilation on redhat5
I am designing a digital filter in behavioral verilog "CIC.v" and it's test bench is "test_CIC.v" using vlogan, vcs,dve.
vlogan went great, the problem is with vcs command , I got this error (...)
I use vcs program from synopsys for verilog code compilation on redhat5
I am designing a digital filter in behavioral verilog "CIC.v" and it's test bench is "test_CIC.v" using vlogan, vcs,dve.
vlogan went great, the problem is with vcs command , I got this error (...)
I have created a compiled library using
vhdlan -w xilinxcorelib -f xilinxcorelib/xilinxcorelib_compile_order.do
When this library is compiled with a verilog file list
(i.e. the verilog file list includes +vhdllib+)
error- Missing library map
Previously analyzed de
+sdfverbose diplays only 10 warnings...there are after there is not any warnings in the log we need to use +sdfverbose switch for vcs simulator...
Hello everybody,
doubt about wich files i need to use in installing vcs tool at openSuse12.2 32b.
Do I need to install the common.tar and (linux.tar or suse32.tar)?
I've installed the suse32.tar but now when I'm executing the vcs in command line the terminal gives this message:
# vcs -f vcs_script.scr (...)
2)run "vcs
*.v" command
then display
"error- Undefined system task
Undefined System Task call to '$vmc_init' "
and other error about $vmc_* task or function
what is wrong ?and what
are the vmc tasks and functions
thank you!
I am trying to simulate a design using modelsim 6.6b PE.
The design contains one secure ip.
The compilation is successful but while loading the design following error is displayed
" Fatal: attempting to load -nodebug design unit."
nodebug designs are not supported. "
fatal error loading design."
Whereas when i use it in vcs it (...)
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