如何使用Debussy与ModelSim做Co-Simulation_百度知道[转帖]ModelSim+Debussy仿真（Verilog） - 海之深 - 博客园
ModelSim+Debussy仿真（Verilog）
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这个人也喜欢海贼王，跟我一样哈，呵呵....
ModelSim+Synplify+Quartus的Altera FPGA的仿真与验证
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百度文库：
1. 目的 当我们使用QuartusII，但是大多数朋友都习惯用Modelsim SE来做仿真，由于Quaruts有很多本身器件的特色，所以造成了在仿真上的麻烦，当然网路上也有一些讲解，但是都是不太系统，特别是对初学者来说，使用的时候还是感到一头雾水。 本文的目的就是一个如何在Quartus 使用Quartus 和Modelsim 仿真的例子。
2．建立QuartusII 工程。 这里目的只是建立一个很简单很简单的QuartusII 的工程，逻辑采用原理图方式绘制。; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilogVeriuser = novas.dll; use by vhdl; Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
RTL部分 (以4 bit counter為例)
counter.v / Verilog
2 (C) OOMusou 2011
4 Filename
: counter.v 5 Simulator
: ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release
: 01/31/ 8 &*/ 9 <span style="color: # &module counter (<span style="color: #
clk,<span style="color: #
rst_n,<span style="color: #
cnt<span style="color: # );<span style="color: # <span style="color: # &input<span style="color: # &input rst_n;<span style="color: # &output [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &reg [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &always@(posedge clk, negedge rst_n) begin<span style="color: #
if (~rst_n) <span style="color: #
cnt &= <span style="color: #'h0;<span style="color: # &
else<span style="color: #
cnt &= cnt + <span style="color: #'b1;
<span style="color: # &end<span style="color: # <span style="color: # &endmodule
Testbench部分
counter_tb.v / Verilog&
2 (C) OOMusou 2011
4 Filename
: counter_tb.v 5 Compiler
: ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release
: 01/31/ 8 &*/ 9 <span style="color: # &module counter_<span style="color: # <span style="color: # &reg<span style="color: # &reg
rst_n;<span style="color: # &wire [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &// 50MHz<span style="color: # &always #(<span style="color: #) clk = ~<span style="color: # <span style="color: # &initial begin<span style="color: #
#<span style="color: #;<span style="color: #
= <span style="color: #'b0;<span style="color: # &
rst_n = <span style="color: #'b0;<span style="color: # &
<span style="color: #
#<span style="color: #;<span style="color: #
rst_n = <span style="color: #'b1;<span style="color: # &
#<span style="color: #5;<span style="color: #
$<span style="color: # &end<span style="color: # <span style="color: # &initial begin<span style="color: #
$fsdbDumpfile("counter.fsdb");<span style="color: #
$fsdbDumpvars(<span style="color: #, counter_tb);<span style="color: # &end<span style="color: # <span style="color: # counter u_counter (<span style="color: #
.clk(clk),<span style="color: #
.rst_n(rst_n),<span style="color: #
.cnt(cnt)<span style="color: # );<span style="color: # <span style="color: # &endmodule
initial begin
#<span style="color: #;
= <span style="color: #'b0;
rst_n = <span style="color: #'b0;
#<span style="color: #;
rst_n = <span style="color: #'b1;
#<span style="color: #5;
一搬來說，若在NC-Verilog做simulation，我們會在testbench內指定結束simulation的時間，不過在ModelSim裡，simulation時間是由ModelSim script控制，在testbench內寫$finish並沒有用，所以會省略$finish時間入下。
initial begin
#<span style="color: #;
= <span style="color: #'b0;
rst_n = <span style="color: #'b0;
#<span style="color: #;
rst_n = <span style="color: #'b1;end&
ModelSim script部分
vlib workvlog counter.vvlog counter_tb.vvsim counter_tbrun 200nsq
建立work library。
vlog counter.vvlog counter_tb.v
編譯RTL：counter.v 與 testbench：counter_tb.v，vlog為modelsim的Verilog compiler。
vsim counter_tb
以counter_tb為top module進行simulation。
命令ModelSim執行200 ns的simulation。
離開ModelSim
執行ModelSim的批次檔
vsim -c -do sim.do
-c 表示ModelSim將以console mode執行，因為在Debussy + ModelSim時，只把ModelSim當成NC-Verilog使用，並沒有用到ModelSim的GUI模式。
-do 表示執行ModelSim script。
D:\<span style="color: #Clare\VerilogLab\ModelSim\counter_verilog&vsim -c -do sim.do Reading C:/Modeltech_6.<span style="color: #e/tcl/vsim/pref.tcl # <span style="color: #.<span style="color: #e# do sim.do # ** Warning: (vlib-<span style="color: #) Library already exists at "work".# Model Technology ModelSim SE vlog <span style="color: #.<span style="color: #e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Compiling module counter# # Top level modules:#
counter# Model Technology ModelSim SE vlog <span style="color: #.<span style="color: #e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Compiling module counter_tb# # Top level modules:#
counter_tb# vsim counter_tb # ** Note: (vsim-<span style="color: #13) Design is being optimized due to module recompilation...# ** Note: (vsim-<span style="color: #65) Due to PLI being present, full design access is being specified.# Loading C:\Modeltech_6.<span style="color: #e\win32/novas.dll# //
ModelSim SE <span style="color: #.<span style="color: #e Feb
<span style="color: # <span style="color: #08 # //# //
Copyright <span style="color: #91-<span style="color: #08 Mentor Graphics Corporation# //
All Rights Reserved.# //# //
THIS WORK CONTAINS TRADE SECRET AND # //
PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //
OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //
AND IS SUBJECT TO LICENSE TERMS.# //# Loading work.counter_tb(fast)# Loading work.counter(fast)# Novas FSDB Dumper for ModelSim, Release <span style="color: #.<span style="color: #v9 (Win95/NT) <span style="color: #/<span style="color: #/<span style="color: #05# Copyright (C) <span style="color: #96 - <span style="color: #04 by Novas Software, Inc.# *Novas* Create FSDB file 'counter.fsdb'# *Novas* Start dumping the scope(counter_tb), layer(<span style="color: #).# *Novas* End of dumping.# ** Note: $finish
: counter_tb.v(<span style="color: #)#
Time: <span style="color: #0 ns
Iteration: <span style="color: #
Instance: /counter_tb
執行Debussy批次檔部份
debussy -<span style="color: #01 counter_tb.v counter.v -ssf counter.fsdb -sswr counter.rc
-2001表示支援Verilog 2001語法
-ssf 載入Debussy dump file
-sswr 載入Debussy signal file
2.RTL與testbench皆使用VHDL
設定ModelSim使用VHDL FLI (因為testbench使用VHDL)
將C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas_fli.dll複製到C:\Modeltech_6.3e\win32\下修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilog;Veriuser = novas.dll; use by vhdlVeriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
複製C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas.vhd到自己的project底下
(為什麼Verilog不需要這個檔，而VHDL需要這個檔，稍後會解釋)
RTL部分 (以4 bit counter為例)
counter.vhd / VHDL
1 -- (C) OOMusou <span style="color: #11 http:// 2 & 3 &-- Filename
: counter.vhd 4 &-- Simulator
: ModelSim <span style="color: #.3e, Debussy <span style="color: #.4 v9 5 &-- Description : ModelSim with debussy 6 &-- Release
: <span style="color: #/<span style="color: #/<span style="color: #11 <span style="color: #.0 7
8 &library IEEE; 9 &use IEEE.std_logic_1164.all;<span style="color: # &use IEEE.std_logic_unsigned.all;<span style="color: # <span style="color: # &entity counter is<span style="color: #
port ( clk
: in std_logic;<span style="color: #
rst_n : in std_logic;<span style="color: #
: out std_logic_vector(<span style="color: # downto <span style="color: #));<span style="color: # &end entity<span style="color: # <span style="color: # &architecture arc of counter is<span style="color: #
signal cnt_r : std_logic_vector(<span style="color: # downto <span style="color: #);<span style="color: # &begin<span style="color: #
process(clk, rst_n) <span style="color: #
begin<span style="color: #
if (rst_n = '<span style="color: #') then<span style="color: #
cnt_r &= "<span style="color: #00";<span style="color: #
elsif rising_edge(clk) then<span style="color: #
cnt_r &= cnt_r + <span style="color: #;<span style="color: #
end if;<span style="color: #
end process;<span style="color: #
<span style="color: #
cnt &= cnt_r;<span style="color: # &end
Testbench部分
counter.vhd / VHDL&
1 -- (C) OOMusou <span style="color: #11 http:// 2 & 3 &-- Filename
: counter_tb.vhd 4 &-- Simulator
: ModelSim <span style="color: #.3e, Debussy <span style="color: #.4 v9 5 &-- Description : ModelSim with debussy 6 &-- Release
: <span style="color: #/<span style="color: #/<span style="color: #10 <span style="color: #.0 7
8 &library IEEE; 9 &use IEEE.std_logic_1164.all;<span style="color: # &use IEEE.std_logic_unsigned.all;<span style="color: # &use work.pkg.all;<span style="color: # <span style="color: # entity counter_tb is <span style="color: # end entity counter_<span style="color: # <span style="color: # architecture arc of counter_tb is<span style="color: #
component counter <span style="color: #
port (<span style="color: #
: in std_logic;<span style="color: #
rst_n : in std_logic;<span style="color: #
: out std_logic_vector(<span style="color: # downto <span style="color: #)<span style="color: #
);<span style="color: #
end component;<span style="color: #
<span style="color: #
signal clk
: std_logic := '<span style="color: #';<span style="color: #
signal rst_n : std_logic := '<span style="color: #';<span style="color: #
signal cnt
: std_logic_vector(<span style="color: # downto <span style="color: #);<span style="color: #
<span style="color: # begin<span style="color: #
process<span style="color: #
begin -- 50MHz<span style="color: #
clk_loop : loop<span style="color: #
clk &= '<span style="color: #';<span style="color: #
wait for <span style="color: #<span style="color: #
clk &= '<span style="color: #';<span style="color: #
wait for <span style="color: #<span style="color: #
end loop clk_<span style="color: #
end process;<span style="color: #
<span style="color: #
process<span style="color: #
begin<span style="color: #
wait for <span style="color: #<span style="color: #
rst_n &= '<span style="color: #';<span style="color: #
end process;<span style="color: #
<span style="color: #
process<span style="color: #
begin<span style="color: #
fsdbDumpfile("counter.fsdb");<span style="color: #
fsdbDumpvars(<span style="color: #, "counter_tb");<span style="color: #
wait;<span style="color: #
end process;<span style="color: #
<span style="color: #
u_counter : counter<span style="color: #
port map (<span style="color: #
=& clk,<span style="color: #
rst_n =& rst_n,<span style="color: #
=& cnt<span style="color: #
);<span style="color: # end&
use work.pkg.all;
這是因為novas.vhd與VHDL FLI的原因，稍後會解釋。
processbegin
fsdbDumpfile("counter.fsdb");
fsdbDumpvars(<span style="color: #, "counter_tb");
wait;end process;
一樣使用fsdbDumpfile()與fsdbDumpvars()兩個Debussy所提供的函數，不過在VHDL FLI並不需要如Verilog PLI一樣加上$。
wait也一定要加上，否則在ModelSim做simulation時會造成無窮回圈無法停止。
ModelSim script部分
vlib workvcom novas.vhdvcom counter.vhdvcom counter_tb.vhdvsim counter_tbrun 200nsq
因為是VHDL，所以全部改用vcom編譯。
其中novas.vhd是從Debussy目錄複製過來的，為什麼需要編譯這個檔案呢?
VHDL FLI (Foreign Language Interface)與Verilog PLI (Programming Language Interface)不同的地方在於，當你自己提供由C寫的function給simulator使用時，Verilog PLI會自己到所提供的dll去找是否有此function，但VHDL FLI需要自己去提供mapping的動作，告訴simulator哪一個function對應dll內那ㄧ個function，novas.vhd就是提供這個mapping的腳色。
若直接使用Debussy所提供的novas.vhd，在執行ModelSim會有以下錯誤訊息。
# ** Warning: (vsim-FLI-<span style="color: #59) Failed to find foreign function 'fliparseVariableInFile' in FLI object file "C:\Modeltech_6.3e\win32/./novas_fli.dll".
意思是novas.vhd定義的fliparseVariableInFile在novas_fli.dll找不到，致於為什麼會有此錯誤，我並不清楚。
將novas.vhd修改成如下所示：
novas.vhd / VHDL
1 package pkg is 2
attribute foreign : string; 3
procedure fsdbDumpfile (file_name : in string); 5
attribute foreign of fsdbDumpfile : procedure is "fliparseTraceInit ./novas_fli.dll"; 6
procedure fsdbDumpvars (depth : in integer; 8
region_name : in string); 9
attribute foreign of fsdbDumpvars : procedure is "fliparsePartial ./novas_fli.dll";<span style="color: # end;<span style="color: # <span style="color: # package body pkg is <span style="color: #
procedure fsdbDumpfile(file_name : in string) is<span style="color: #
begin<span style="color: #
assert false report "ERROR : foreign subprogram not called" severity note;<span style="color: #
end;<span style="color: #
<span style="color: #
procedure fsdbDumpvars(depth : in integer;<span style="color: #
region_name : in string) is<span style="color: #
begin<span style="color: #
assert false report "ERROR : foreign subprogram not called" severity note;<span style="color: #
end;<span style="color: # end; <span style="color: # <span style="color: # entity novas is end; <span style="color: # <span style="color: # architecture novas_arch of novas is<span style="color: #
attribute foreign : string;<span style="color: #
attribute foreign of novas_arch : architecture is "fliparseCommand novas_fli.dll";<span style="color: # begin<span style="color: # end;<span style="color: #
也就是僅留下fsdbDumpfile()與fsdbDumpvars()兩個function，其他的都刪除。
根據我使用Debussy的經驗，只要留這兩個function就夠用了，其他Debussy的function我還真的沒用過。
在novas.vhd也看到了這些是定義在pkg這個package下，所以在counter_tb.vhd必須use work.pkg.all。
執行ModelSim的批次檔
vsim -c -do sim.do
D:\0Clare\VerilogLab\ModelSim\counter_vhdl&vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # <span style="color: #.3e# do sim.do # ** Warning: (vlib-<span style="color: #) Library already exists at "work".# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Compiling package pkg# -- Compiling package body pkg# -- Loading package pkg# -- Compiling entity novas# -- Compiling architecture novas_arch of novas# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Compiling entity counter# -- Compiling architecture arc of counter# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Loading package pkg# -- Compiling entity counter_tb# -- Compiling architecture arc of counter_tb# vsim counter_tb # Loading C:\Modeltech_6.3e\win32/novas.dll# //
ModelSim SE <span style="color: #.3e Feb
<span style="color: # <span style="color: #08 # //# //
Copyright <span style="color: #91-<span style="color: #08 Mentor Graphics Corporation# //
All Rights Reserved.# //# //
THIS WORK CONTAINS TRADE SECRET AND # //
PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //
OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //
AND IS SUBJECT TO LICENSE TERMS.# //# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.pkg(body)# Loading C:\Modeltech_6.3e\win32/./novas_fli.dll# Loading work.counter_tb(arc)# Loading work.counter(arc)# Novas FSDB Dumper for ModelSim <span style="color: #.4 (FLI), Release <span style="color: #.4v9 (Win95/NT) <span style="color: #/<span style="color: #/<span style="color: #05# Copyright (C) <span style="color: #96 - <span style="color: #04 by Novas Software, Inc.# *Novas* Create FSDB file 'counter.fsdb'
執行Debussy批次檔部份
debussy –vhdl –93 novas.vhd counter_tb.vhd counter.vhd –top counter_tb -ssf counter.fsdb -sswr counter.rc
-vhdl 表示支援VHDL語法，因為Debussy預設支援Verilog
-93 表示支援VHDL 93的語法
-top 指定top module，在Verilog可以不指定top，Debussy可以自動判斷而抓到top module，但是VHDL沒辦法，需要自己指定，若不指定，待會會有GUI要你手動挑選top module
3.RTL使用VHDL，testbench使用Verilog
設定ModeSim使用Verilog PLI (因為testbench使用Verilog)
將C:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\novas.dll複製到C:\Modeltech_6.3e\win32\下修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilogVeriuser = novas.dll; use by vhdl; Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
RTL部分 (以4 bit counter為例)
counter.vhd / VHDL
1 -- (C) OOMusou <span style="color: #11 http:// 2 & 3 &-- Filename
: counter.vhd 4 &-- Simulator
: ModelSim <span style="color: #.3e, Debussy <span style="color: #.4 v9 5 &-- Description : ModelSim with debussy 6 &-- Release
: <span style="color: #/<span style="color: #/<span style="color: #11 <span style="color: #.0 7
8 &library IEEE; 9 use IEEE.std_logic_1164.all;<span style="color: # use IEEE.std_logic_unsigned.all;<span style="color: # <span style="color: # entity counter is<span style="color: #
port ( clk
: in std_logic;<span style="color: #
rst_n : in std_logic;<span style="color: #
: out std_logic_vector(<span style="color: # downto <span style="color: #));<span style="color: # end entity<span style="color: # <span style="color: # architecture arc of counter is<span style="color: #
signal cnt_r : std_logic_vector(<span style="color: # downto <span style="color: #);<span style="color: # begin<span style="color: #
process(clk, rst_n) <span style="color: #
begin<span style="color: #
if (rst_n = '<span style="color: #') then<span style="color: #
cnt_r &= "<span style="color: #00";<span style="color: #
elsif rising_edge(clk) then<span style="color: #
cnt_r &= cnt_r + <span style="color: #;<span style="color: #
end if;<span style="color: #
end process;<span style="color: #
<span style="color: #
cnt &= cnt_r;<span style="color: # end
Testbench部分
counter_tb.v / Verilog&
2 (C) OOMusou 2011
4 Filename
: counter_tb.v 5 Compiler
: ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release
: 01/31/ 8 &*/ 9 <span style="color: # &module counter_<span style="color: # <span style="color: # &reg<span style="color: # &reg
rst_n;<span style="color: # &wire [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &// 50MHz<span style="color: # &always #(<span style="color: #) clk = ~<span style="color: # <span style="color: # &initial begin<span style="color: #
#<span style="color: #;<span style="color: #
= <span style="color: #'b0;<span style="color: # &
rst_n = <span style="color: #'b0;<span style="color: # &
<span style="color: #
#<span style="color: #;<span style="color: #
rst_n = <span style="color: #'b1;<span style="color: # &
#<span style="color: #5;<span style="color: #
$<span style="color: # &end<span style="color: # <span style="color: # &initial begin<span style="color: #
$fsdbDumpfile("counter.fsdb");<span style="color: #
$fsdbDumpvars(<span style="color: #, counter_tb);<span style="color: # &end<span style="color: # <span style="color: # counter u_counter (<span style="color: #
.clk(clk),<span style="color: #
.rst_n(rst_n),<span style="color: #
.cnt(cnt)<span style="color: # );<span style="color: # <span style="color: # &endmodule
initial begin
$fsdbDumpfile("counter.fsdb");
$fsdbDumpvars(<span style="color: #, counter_tb);end
$fsdbDumpvars()的第一個參數是填1不是0，若填0會產生以下warning，不過並不影響最後fsdb的結果。
# ** Warning: Unknown scope type: counter_tb.u_counter <span style="color: #10#
: counter_tb.v(<span style="color: #)#
Time: <span style="color: # ns
Iteration: <span style="color: #
Instance: /counter_tb# ** Warning: Unknown scope type: counter_tb.u_counter <span style="color: #10#
: counter_tb.v(<span style="color: #)#
Time: <span style="color: # ns
Iteration: <span style="color: #
Instance: /counter_tb# *Novas* End of dumping.
ModelSim script部分
vlib workvcom counter.vhdvlog counter_tb.vvsim counter_tbrun 200nsq
VHDL使用vcom編譯，Verilog使用vlog編譯。
執行ModelSim的批次檔
vsim -c -do sim.do
D:\0Clare\VerilogLab\ModelSim\counter_vhdl_verilog&vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # <span style="color: #.3e# do sim.do # ** Warning: (vlib-<span style="color: #) Library already exists at "work".# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Compiling entity counter# -- Compiling architecture arc of counter# Model Technology ModelSim SE vlog <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Compiling module counter_tb# # Top level modules:#
counter_tb# vsim counter_tb # Loading C:\Modeltech_6.3e\win32/novas.dll# //
ModelSim SE <span style="color: #.3e Feb
<span style="color: # <span style="color: #08 # //# //
Copyright <span style="color: #91-<span style="color: #08 Mentor Graphics Corporation# //
All Rights Reserved.# //# //
THIS WORK CONTAINS TRADE SECRET AND # //
PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //
OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //
AND IS SUBJECT TO LICENSE TERMS.# //# Loading work.counter_tb(fast)# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.counter(arc)# Novas FSDB Dumper for ModelSim, Release <span style="color: #.4v9 (Win95/NT) <span style="color: #/<span style="color: #/<span style="color: #05# Copyright (C) <span style="color: #96 - <span style="color: #04 by Novas Software, Inc.# *Novas* Create FSDB file 'counter.fsdb'# *Novas* Start dumping the scope(counter_tb), layer(<span style="color: #).# ** Warning: Unknown scope type: counter_tb.u_counter <span style="color: #10#
: counter_tb.v(<span style="color: #)#
Time: <span style="color: # ns
Iteration: <span style="color: #
Instance: /counter_tb# ** Warning: Unknown scope type: counter_tb.u_counter <span style="color: #10#
: counter_tb.v(<span style="color: #)#
Time: <span style="color: # ns
Iteration: <span style="color: #
Instance: /counter_tb# *Novas* End of dumping.D:\0Clare\VerilogLab\ModelSim\counter_vhdl_verilog&vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # <span style="color: #.3e# do sim.do # ** Warning: (vlib-<span style="color: #) Library already exists at "work".# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Compiling entity counter# -- Compiling architecture arc of counter# Model Technology ModelSim SE vlog <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Compiling module counter_tb# # Top level modules:#
counter_tb# vsim counter_tb # ** Note: (vsim-<span style="color: #13) Design is being optimized due to module recompilation...# ** Note: (vsim-<span style="color: #65) Due to PLI being present, full design access is being specified.# Loading C:\Modeltech_6.3e\win32/novas.dll# //
ModelSim SE <span style="color: #.3e Feb
<span style="color: # <span style="color: #08 # //# //
Copyright <span style="color: #91-<span style="color: #08 Mentor Graphics Corporation# //
All Rights Reserved.# //# //
THIS WORK CONTAINS TRADE SECRET AND # //
PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //
OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //
AND IS SUBJECT TO LICENSE TERMS.# //# Loading work.counter_tb(fast)# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.counter(arc)# Novas FSDB Dumper for ModelSim, Release <span style="color: #.4v9 (Win95/NT) <span style="color: #/<span style="color: #/<span style="color: #05# Copyright (C) <span style="color: #96 - <span style="color: #04 by Novas Software, Inc.# *Novas* Create FSDB file 'counter.fsdb'# *Novas* Start dumping the scope(counter_tb), layer(<span style="color: #).# *Novas* End of dumping.
執行Debussy批次檔部份
vhdlcom -<span style="color: # counter.vhdvericom -<span style="color: #01 counter_tb.vdebussy -lib work -top counter_tb -ssf counter.fsdb -sswr counter.rc
若RTL與testbench同時包含Verilog與VHDL，Debussy就無法直接開啟，必須先將Verilog與VHDL分別編譯成lib，然後才可開啟。
VHDL使用vhdlcom作編譯，-93表示支援VHDL 93的語法，Verilog使用vericom作編譯，-2001表示支援Verilog 2001語法，vhdlcom與vericom預設都會編譯在work這個lib下，所以debussy開啟時需用-lib指定使用work這個lib，並用-top指定top module，這樣才可開啟mixed-language的design。
4.RTL使用Verilog，testbench使用VHDL
設定ModelSim使用VHDL FLI (因為testbench使用VHDL)
將C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas_fli.dll複製到C:\Modeltech_6.3e\win32\下修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications; Veriuser = veriuser.sl; use by verilog;Veriuser = novas.dll; use by vhdlVeriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
RTL部分 (以4 bit counter為例)
counter.v / Verilog
2 (C) OOMusou 2011
4 Filename
: counter.v 5 Simulator
: ModelSim 6.3e, Debussy 5.4 v9 6 Description : ModelSim with debussy 7 Release
: 01/31/ 8 &*/ 9 <span style="color: # &module counter (<span style="color: #
clk,<span style="color: #
rst_n,<span style="color: #
cnt<span style="color: # );<span style="color: # <span style="color: # &input<span style="color: # &input rst_n;<span style="color: # &output [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &reg [<span style="color: #:<span style="color: #]<span style="color: # <span style="color: # &always@(posedge clk, negedge rst_n) begin<span style="color: #
if (~rst_n) <span style="color: #
cnt &= <span style="color: #'h0;<span style="color: # &
else<span style="color: #
cnt &= cnt + <span style="color: #'b1;
<span style="color: # &end<span style="color: # <span style="color: # &endmodule
Testbench部分
counter.vhd / VHDL&
1 -- (C) OOMusou <span style="color: #11 http:// 2
3 -- Filename
: counter_tb.vhd 4 -- Simulator
: ModelSim <span style="color: #.3e, Debussy <span style="color: #.4 v9 5 -- Description : ModelSim with debussy 6 -- Release
: <span style="color: #/<span style="color: #/<span style="color: #10 <span style="color: #.0 7
8 library IEEE; 9 use IEEE.std_logic_1164.all;<span style="color: # use IEEE.std_logic_unsigned.all;<span style="color: # use work.pkg.all;<span style="color: # <span style="color: # entity counter_tb is <span style="color: # end entity counter_<span style="color: # <span style="color: # architecture arc of counter_tb is<span style="color: #
component counter <span style="color: #
port (<span style="color: #
: in std_logic;<span style="color: #
rst_n : in std_logic;<span style="color: #
: out std_logic_vector(<span style="color: # downto <span style="color: #)<span style="color: #
);<span style="color: #
end component;<span style="color: #
<span style="color: #
signal clk
: std_logic := '<span style="color: #';<span style="color: #
signal rst_n : std_logic := '<span style="color: #';<span style="color: #
signal cnt
: std_logic_vector(<span style="color: # downto <span style="color: #);<span style="color: #
<span style="color: # begin<span style="color: #
process<span style="color: #
begin -- 50MHz<span style="color: #
clk_loop : loop<span style="color: #
clk &= '<span style="color: #';<span style="color: #
wait for <span style="color: #<span style="color: #
clk &= '<span style="color: #';<span style="color: #
wait for <span style="color: #<span style="color: #
end loop clk_<span style="color: #
end process;<span style="color: #
<span style="color: #
process<span style="color: #
begin<span style="color: #
wait for <span style="color: #<span style="color: #
rst_n &= '<span style="color: #';<span style="color: #
end process;<span style="color: #
<span style="color: #
process<span style="color: #
begin<span style="color: #
fsdbDumpfile("counter.fsdb");<span style="color: #
fsdbDumpvars(<span style="color: #, "counter_tb");<span style="color: #
wait;<span style="color: #
end process;<span style="color: #
<span style="color: #
u_counter : counter<span style="color: #
port map (<span style="color: #
=& clk,<span style="color: #
rst_n =& rst_n,<span style="color: #
=& cnt<span style="color: #
);<span style="color: # end&
ModelSim script部分
vlib workvcom novas.vhdvlog counter.vvcom counter_tb.vhdvsim counter_tbrun 200nsq
VHDL使用vcom編譯，Verilog使用vlog編譯。
執行ModelSim的批次檔
vsim -c -do sim.do
D:\0Clare\VerilogLab\ModelSim\counter_verilog_vhdl&vsim -c -do sim.do Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl # <span style="color: #.3e# do sim.do # ** Warning: (vlib-<span style="color: #) Library already exists at "work".# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Compiling package pkg# -- Compiling package body pkg# -- Loading package pkg# -- Compiling entity novas# -- Compiling architecture novas_arch of novas# Model Technology ModelSim SE vlog <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Compiling module counter# # Top level modules:#
counter# Model Technology ModelSim SE vcom <span style="color: #.3e Compiler <span style="color: #08.02 Feb
<span style="color: # <span style="color: #08# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Loading package pkg# -- Compiling entity counter_tb# -- Compiling architecture arc of counter_tb# vsim counter_tb # Loading C:\Modeltech_6.3e\win32/novas.dll# //
ModelSim SE <span style="color: #.3e Feb
<span style="color: # <span style="color: #08 # //# //
Copyright <span style="color: #91-<span style="color: #08 Mentor Graphics Corporation# //
All Rights Reserved.# //# //
THIS WORK CONTAINS TRADE SECRET AND # //
PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //
OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //
AND IS SUBJECT TO LICENSE TERMS.# //# Loading std.standard# Loading ieee.std_logic_1164(body)# Loading ieee.std_logic_arith(body)# Loading ieee.std_logic_unsigned(body)# Loading work.pkg(body)# Loading C:\Modeltech_6.3e\win32/./novas_fli.dll# Loading work.counter_tb(arc)# Loading work.counter(fast)# Novas FSDB Dumper for ModelSim <span style="color: #.4 (FLI), Release <span style="color: #.4v9 (Win95/NT) <span style="color: #/<span style="color: #/<span style="color: #05# Copyright (C) <span style="color: #96 - <span style="color: #04 by Novas Software, Inc.# *Novas* Create FSDB file 'counter.fsdb'
執行Debussy批次檔部份
vericom -<span style="color: #01 counter.vvhdlcom -<span style="color: # novas.vhd counter_tb.vhddebussy -lib work -top counter_tb -ssf counter.fsdb -sswr counter.rc
完整程式碼下載 (RTL與testbench皆使用Verilog) (RTL與testbench皆使用VHDL) (RTL使用VHDL，testbench使用Verilog) (RTL使用Verilog，testbench使用VHDL)
Conclusion本文介紹了Debussy與ModelSim的Co-Simulation，這兩個工具的合作，可以發揮ModelSim能Verilog與VHDL一起simulation的優點，又可發揮Debussy的trace與debug的功力；並且實際示範了2種HDL語言交互simulation的方法，其中包含了一些小技巧。
在Quartus II也允許這種跨語言的方式作synthesis，或許你會問，為什麼要搞的這麼複雜?乖乖只用Verilog或只用VHDL就好了，但現實上，這兩個HDL語言佔有率幾乎一半一半，無論是工作上也好，或者看書網路上找資源，遇到Verilog或者VHDL的機會仍相當多，像我是Verilog比較熟，但有些IP是用VHDL開發(無論是買來的或者網路抓的)，所以VHDL也要多少懂一點，最少要能一起Co-Simulation，雖然重要的是硬體的設計，但多懂一種語言也不是壞事。
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