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37Astro的布局与布线_经验总结-4
Astro流程注意事项；1、目录和文件管理：在主目录下面建立以下几个主要；1）backend主要用来存放后端人员编写的TD；2）frontend存放前端的.v以及.sdc文；3）lib存放referencelibrary，；4）scripts存放参考脚本文件；5）report从Astro倒出的数据放在这里，；6）work工作目录，从这里启动Astro；7）s
Astro 流程注意事项 1、目录和文件管理：在主目录下面建立以下几个主要的工作目录1）backend
主要用来存放后端人员编写的TDF文件2）frontend
存放前端的.v以及.sdc文件3）lib
存放reference library ，技术文件，以及需要建立的主库4）scripts
存放参考脚本文件5）report
从Astro倒出的数据放在这里，比如.vg .sdf .spef等文件以及每次时序报告6）work
工作目录，从这里启动Astro。存放日志、命令历史、时钟树Buffer等文件，这里记录着Astro工作的轨迹。每次需要重新开始做的时候，可以把这里面自动生成的cmd 以及log等各种文件删除7）star
为StarRCXT抽取时序参数而建立的工作目录，在这里启动StarRCXT2、TDF文件注意！Astro对TDF有特定的识别方式，后端人员在编写TDF文件时必须符合这个格式要求，否则floorplan时可能得不到符合预期的结果，如正方形变长方形。一般按照order来写，这样比较方便。Astro中的PAD order如下图所示，假设有208个PAD： 特别注意CORNER的order，另外每边都要从1到53（或从53到1），不能随意。 如果不是紧密排放，那么就按照location来写，这样能控制相邻PAD之间距离，也需要注意CORNER的位置（此时是坐标位置，不是顺序位置）。 3、关于时钟信号PAD 摆放：一般放在某边的中间位置，如上图中bottom的第25号PAD，这样时钟树能生长的比较正，有利于clock skew的降低。关于电源PAD，要均匀分布，这样能使供电充分；另外电源PAD不要放在每边的开始以及结束处，原因是可能造成不能直连到core ring 电源环上，影响布线。 4、关于电源strap放置。macro单元边上放strap，使该宏模块周围的standard cell 由这些strap供电，而不用跨过macro再连到core ring上，这能省下macro 上层的布线资源给信号线用。可以通过route setup 里面的 create route guide
把no automatic preroute on layer M1,M2,M3,M4,M5,M6全选上。 5、电源ring和strap布置完毕，preroute电源（macro,,pad，此时不必给标准单元也连接电源）后，要进行verify PGconnectivity！！！确保以后做的事情不是在浪费时间。 6、在做placement时，如果可利用面积比较大，（core的使用率不是特别大），推荐在strap下面不要放置标准单元；在strap下面不放标准单元的方法：先在place common options里选择no standard cells under preroute of M1-M6;然后再 axgPlaceDesign。 7、时钟树综合结束，开始布线，第一步是连接标准单元的电源和地，之前其他的大步骤中都不需要连接标准单元的电源线和地线（这和synopsys教程不同，这样能节省更多时间）连接结束后同样要进行verify PGconnectivity！ 8、布局布线完毕，timing report没有问题之后，可以提取hierarchy netlist 和 SDF 以及SPEF文件给前端人员做静态仿真（formality 以及PrimeTime）；DFM结束之后再报timing和做DRC，之后再次提取这些文件做后仿，此时包含了dummy元素的影响，最接近实际。一般比较大的case不做动态仿真，因为比较消耗时间。 9、FillWireTrack时，不要选择self，多一个FILL VIEW比较好，只是注意后面用StarRCXT抽取参数时，cmd文件要保证抽取的参数包含了FILL的寄生参数影响；以及在倒gds文件时把FILL选上。选择2到3倍间距，这样既能保证金属密度，又不容易有minispacing错误 10、前端网表更新之后，要重新开始整个流程：把Astro 退出，删除主库，删除 .cmd以及 .log文件，然后再次建库。 11、为了验证前端网表是不是有物理错误，可以先不选择Timing Driven，而仅仅布局布线，确定无误了，再从Timing Setup这步开始Timing Driven 的布局布线流程。 12、关于时序面板的设置。这个是时序驱动的布局布线中非常重要而又容易忽略的。CTS之前设置如下图所示： 此时Ignore Clock Uncertainty不能选择，应该采用由SDC文件设置的Uncertainty。 CTS结束之后面板设置改变为如下： 此时不能Ignore Propagated Clock；时钟树综合完了Clock Uncertainty就确定了，所以Ignore Clock Uncertainty不能选上。时序面板中的Model选项卡在布线前后也需要改变，布线前的Net Delay Model是 Elmore，这时计算延时是用的Virtural_RC，是近似的而不是精确的，如下图： 布线结束之后，就应该把上述模型选择为AWE或者Arnoldi，这时计算的延时就是比较精确的。如下图： 包含各类专业文献、外语学习资料、应用写作文书、高等教育、生活休闲娱乐、37Astro的布局与布线_经验总结等内容。　
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Astro详细的布局布线流程，内含详细的操作步骤macro_flow
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3秒自动关闭窗口From Wikipedia, the free encyclopedia
In , physical design is a step in the standard design cycle which follows after the . At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called . This step is usually split into several sub-steps, which include both design and verification and validation of the layout.
Modern day
(IC) design is split up into Front-end design using HDLs, Verification, and Back-end Design or Physical Design. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs.
Each of the phases mentioned above have Design Flows associated with them. These Design Flows lay down the process and guide-lines/framework for that phase. Physical Design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of Silicon wafer used, the standard-cells used, the layout rules (like DRC in VLSI), etc.
Physical design steps within the IC design flow
Typically, the IC physical design is categorised into
& Semi-Custom Design.
Full-Custom: Designer has full flexibility on the layout design, no predefined cells are used.
Semi-Custom: Pre-designed library cells (preferably tested with ) are used, designer has flexibility in placement of the cells & routing.
One can refer
for Full Custom design and
for Semi-Custom design flows.The reason being that one have the flexibility to design/modify design blocks from Vendor provided libraries in ASIC. This flexibility is missing for Semi-Custom flows like FPGA (e.g. ).
back-end flow
The main steps in the
physical design flow are:
Design Netlist (after synthesis)
Floorplanning
Partitioning
Clock-tree Synthesis (CTS)
Physical Verification
GDS II Generation
These steps are just the basic. There are detailed PD flows that are used depending on the Tools used and the methodology/technology. Some of the tools/software used in the back-end design are :
Cadence (Cadence Encounter RTL Compiler, Encounter Digital Implementation, Cadence Voltus IC Power Integrity Solution, Cadence Tempus Timing Signoff Solution)
Synopsys (Design Compiler, IC Compiler)
Magma (BlastFusion, etc.)
Mentor Graphics (Olympus SoC, IC-Station, Calibre)
A more detailed Physical Design Flow is shown below. Here you can see the exact steps and the tools used in each step outlined.
The ASIC physical design flow uses the technology libraries that are provided by the fabrication houses. Technologies are commonly classified according to minimal feature size. Standard sizes, in the order of miniaturization, are 2, 1μm , 0.5μm , 0.35μm, 0.25μm, 180, 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 18nm, 14nm, etc. They may be also classified according to major manufacturing approaches: , ,
process, etc.
Physical design is based on a netlist which is the end result of the Synthesis process. Synthesis converts the RTL design usually coded in VHDL or Verilog HDL to gate-level descriptions which the next set of tools can read/understand. This netlist contains information on the cells used, their interconnections, area used, and other details. Typical synthesis tools are:
Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS)
Synopsys Design Compiler
During the synthesis process, constraints are applied to ensure that the design meets the required functionality and speed (specifications). Only after the netlist is verified for functionality and timing it is sent for the physical design flow.
The first step in the physical design flow is Floorplanning. Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.
Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floorplanning takes into account the macros used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floorplanning also decides the IO structure, aspect ratio of the design. A bad floorplan will lead to waste-age of die area and routing congestion.
In many design methodologies, Area and Speed are considered to be things that should be traded off against each other. The reason this is so is probably because there are limited routing resources, and the more routing resources that are used, the slower the design will operate. Optimizing for minimum area allows the design to use fewer resources, but also allows the sections of the design to be closer together. This leads to shorter interconnect distances, less routing resources to be used, faster end-to-end signal paths, and even faster and more consistent place and route times. Done correctly, there are no negatives to floorplanning.
As a general rule, data-path sections benefit most from floorplanning, and random logic, state machines, and other non-structured logic can safely be left to the placer section of the place and route software.
Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and Muxes.
Partitioning is a process of dividing the chip into small blocks. This is done mainly to separate different functional blocks and also to make placement and routing easier. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. These modules are linked together in the main module called the TOP LEVEL module. This kind of partitioning is commonly referred to as Logical Partitioning.
Before the start of placement optimization all Wire Load Models (WLM) are removed. Placement uses RC values from Virtual Route (VR) to calculate timing. VR is the shortest Manhattan distance between two pins. VR RCs are more accurate than WLM RCs.
Placement is performed in four optimization phases:
Pre-placement optimization
In placement optimization
Post Placement Optimization (PPO) before clock tree synthesis (CTS)
PPO after CTS.
Pre-placement Optimization optimizes the netlist before placement, HFNs are collapsed. It can also downsize the cells.
In-placement optimization re-optimizes the logic based on VR. This can perform cell sizing, cell moving, cell bypassing, net splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of setup fixing, incremental timing and congestion driven placement.
Post placement optimization before CTS performs netlist optimization with ideal clocks. It can fix setup, hold, max trans/cap violations. It can do placement optimization based on global routing. It re does HFN synthesis.
Post placement optimization after CTS optimizes timing with propagated clock. It tries to preserve clock skew.
Ideal clock before CTS
The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not propagated before CTS as shown in the picture. After CTS hold slack should improve. Clock tree begins at .sdc defined clock source and ends at stop pins of flop. There are two types of stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins are ignored for timing analysis. If clock is divided then separate skew analysis is necessary.
Global skew achieves zero skew between two synchronous pins without considering logic relationship.
Local skew achieves zero skew between two synchronous pins while considering logic relationship.
If clock is skewed intentionally to improve setup slack then it is known as useful skew.
Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the constraints.
Clock After CTS
In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack. In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added.
There are two types of
in the physical design process, global routing and detailed routing. Global routing allocates routing resources that are used for connections. Detailed routing assigns routes to specific metal layers and routing tracks within the global routing resources.
Physical verification checks the correctness of the generated layout design. This includes verifying that the layout
Complies with all technology requirements – Design Rule Checking (DRC)
Is consistent with the original netlist – Layout vs. Schematic (LVS)
Has no antenna effects – Antenna Rule Checking
This also includes density verification at the full chip level...Cleaning density is a very critical step in the lower technology nodes
Complies with all electrical requirements – Electrical Rule Checking (ERC).
N. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer (1998),
Mehrotra, A Van Ginneken, Lukas P P P; Trivedi, Yatin. , IEEE Conference Publications,
A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2011), , p. 27.Astro的布局与布线流程_百度文库
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